RX_START_THLD=Val_0x0, TX_EMPTY_BUF_THLD=Val_0b000, RX_BUF_THLD=Val_0x0, TX_START_THLD=Val_0x0
Data Buffer Threshold Control Register
TX_EMPTY_BUF_THLD | Transmit Buffer Threshold Value This field controls the number of empty locations (or above) in the Tx FIFO. The supported values for this field are: 0 (Val_0b000): 1 1 (Val_0b001): 4 2 (Val_0b010): 8 3 (Val_0b011): 16 4 (Val_0b100): 32 5 (Val_0b101): 64 |
RX_BUF_THLD | Receive Buffer Threshold Value This field controls the number of entries (or above) in the Rx FIFO. The supported values for this field are: 0 (Val_0x0): 1 1 (Val_0x1): 4 2 (Val_0x2): 8 3 (Val_0x3): 16 4 (Val_0x4): 32 5 (Val_0x5): 64 |
TX_START_THLD | Transfer Start Threshold Value In Master mode of operation when the I3C is set up to initiate a write transfer, it waits until either one of the following conditions are met before it initiates the write transfer on the I3C Interface:
0 (Val_0x0): 1 1 (Val_0x1): 4 2 (Val_0x2): 8 3 (Val_0x3): 16 4 (Val_0x4): 32 5 (Val_0x5): 64 |
RX_START_THLD | Receive Start Threshold Value In Master mode of operation when the I3C is set up to initiate a read transfer, it waits until either one of the conditions are met before it initiates the read transfer on the I^3C interface.
0 (Val_0x0): 1 1 (Val_0x1): 4 2 (Val_0x2): 8 3 (Val_0x3): 16 4 (Val_0x4): 32 5 (Val_0x5): 64 |